Since the invention of one-transistor-one-capacitor (ITIC) DRAM cell in the late 1960s as described in U.S. Pat. No. 3,387,286, the technology has been advancing continuously and is now approaching the sub-100 nm generation. To go beyond the sub-100 nm generation, there are many challenges and scaling issues as described in publication “Challenges and future directions for the scaling of dynamic random-access memory (DRAM)”, J. A. Mandelman et. al., IBM J. Res. & Dev. Vol 46 No. 2/3 March/May 2002. Some of these challenges and scaling issues include process and capacitance challenges and voltage-scaling and leakage issues.
Publication “International Technology Roadmap for Semiconductor 2004 Update” sets out projected key parameters of different emerging research memory devices with present day memory technologies as benchmarks. In particular, for present day memory technology such as the ITIC DRAM, the programming time has been indicated to be less than 15 ns and the retention time to be approximately 64 ms.
Several new memory structures have been proposed for DRAM applications. A memory structure that utilizes direct tunneling into silicon nanocrystal (nc-Si) for producing bistability in the conduction of a transistor channel and exhibiting quasi-non-volatile characteristics has been proposed in publication “A silicon nanocrystals based memory”, Sandip Tiwari et. al., Appl. Phys. Lett. 68 (10), 4 March 1996. The memory structure comprises a thin tunneling oxide of approximately 1.1 to 1.8 nm in thickness which separates the inversion surface of an n-channel silicon field-effect transistor (FET) from a distributed film of nc-Si that covers the entire surface channel region. The memory structure further comprises a thicker tunneling oxide of approximately 4.5 nm or higher which separates the nc-Si from the control gate of the FET. An injection of an electron from the inversion layer into the nc-Si occurs via direct tunneling when the control gate is forward biased with respect to the source and drain. The resulting stored charge screens the gate charge and reduces the conduction in the inversion layer, i.e., it effectively shifts the threshold voltage of the device to be more positive. However, the programming time of the memory structure is approximately 100 ns which is too slow for DRAM applications.
Recently, a new memory structure which has a relatively short programming time of about 3 ns was proposed in publication “A simple 1-transistor capacitor-less memory cell for high performance embedded DRAMs”, Pierre C. Fazan et. al., IEEE 2002 Custom Integrated Circuits Conference”. However such a memory structure is based on silicon on insulator (SOI) technology which is expensive, and the retention time is less than 10 s.
Therefore, there is still a need for an alternative DRAM structure that has good reliability characteristics, a fast programming time and a long retention time, which could tremendously reduce the power dissipation required for data refreshment.